IEEE

Fig. 6.

Proof

Comparison of (a) transverse stress profiles and (b) STI stress-induced hole mobility variations for planar versus trigate (WSTRIPE = 20 nm) bulk

MOSFETs using Taurus 3-D [11]. The silicon stripe height is 10 nm for the trigate bulk MOSFETs, which provides for more uniform channel mobility because

of reduced STI-induced channel stress.

Fig. 7.

CESL-induced stress distribution in planar and trigate bulk MOSFETs. The CESL is assumed to be a 30-nm-thick silicon nitride with 2-GPa tensile

SUN et al.: STUDY OF PLANAR MOSFET, SOI FinFET, AND TRIGATE MOSFET DESIGNS

5

Fig. 8. Examples of simulated gate electrodes with different LER profiles.

FinFET, and planar bulk MOSFET.

LG = 20 nm, and tSi = 0.6 LG =

12 nm.

IEEE

Fig. 9. LER-induced variation in trigate bulk MOSFET, SOI FinFET, and

planar bulk MOSFET. LG = 20 nm, and tSi = 0.6 LG = 12 nm.

142 the same LER as the gate electrode to simulate the worst case

143 scenario; thus, Le will have the same roughness profile as

144

LG. The RDF profiles are generated using kinetic Monte Carlo

145 simulations [9] on the MOSFET structures with gate LER.

146

Three-dimensional device simulations are performed for the

147 optimized nominal designs to investigate the effects of LER

148 only and also to investigate the effects of LER, together with

149

RDF, in the source/drain and channel regions.

150

Fig. 9 shows the gate LER-induced VT variations (σVT )

151 for the SOI FinFET, planar bulk MOSFET, and trigate bulk

152

MOSFET with tSi = 0.6 LG. The variation is smallest for the

153 trigate bulk MOSFET design due to its superior electrostatic

154 integrity. The SOI FinFET has VT variation comparable to that

155 of the planar bulk MOSFET. This is because the two sidewall

156 gates of the FinFET have discrete different gate lengths due to

Fig. 11. Effect of tSi on LERand RDFinduced variations. LG = 20 nm.

157

gate LWR, whereas the effects of gate LWR on planar bulk

158

MOSFETs are somewhat averaged across the channel width.

(a) tSi = 0.6 LG = 12 nm. (b) tSi = 0.8 LG = 16 nm.

159

VT variations due to the presence of both LER and RDF are

160 shown in Fig. 10. VT lowering (where

VT is equal to the

gradient regions increases with smaller WSTRIPE [12] and 167

161

VT value of the nominal design subtracted by the mean VT

also because of larger LER-induced variation, the SOI FinFET 168

162 value of the MOSFET structures with gate LER and RDF)

does not provide for reduced random variation, as compared 169

163 is smallest for the trigate bulk MOSFET due to its superior

with the trigate bulk MOSFET design, although there are no 170

164 electrostatic integrity. Overall, the trigate bulk MOSFET also

channel dopants in the SOI FinFET. Fig. 11 shows the effect 171

165 shows comparable random VT

variation as the SOI FinFET.

of tSi on the random variation. For the trigate bulk MOSFET, 172

166

Because VT variation induced

by RDF

in the source/drain

tSi = 0.6 LG yields the smallest random variation, whereas 173

177

V. CONCLUSION

pp. 2840–2842, Nov. 2009.

208

[8] A. Hokazono, H. Itokawa, N. Kusunoki, I. Mizushima,

S. Inaba, 209

Symp. Tech. Dig., 2008, pp. 112–113.

212

stress,” in IEDM Tech. Dig., 1999, pp. 827–830.

217

[11] Taurus User’s Manual, Synopsys, Inc., Mountain View, CA.

218

AQ1

Proc. IEEE Silicon Nanoelectron. Workshop, 2006, pp. 137–138.

221

185

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[3] R.-H. Yan, A. Ourmazd, and K. F. Lee, “Scaling the Si MOSFET: From

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[4] K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, and Y. Arimoto, “Scaling

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